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  1 copyright ? cirrus logic, inc. 1999 (all rights reserved) cirrus logic, inc. crystal semiconductor products division p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs5529 16-bit, programmable ds adc with 6-bit latch features l delta-sigma analog-to-digital converter - linearity error: 0.0015%fs - noise free resolution: 16-bits l 2.5 v bipolar/unipolar buffered input range l 6-bit output latch l eight digital filters - selectable output word rates - output settles in one conversion cycle - 50/60 hz 3 hz simultaneous rejection l simple three-wire serial interface - spi? and microwire? compatible - schmitt trigger on serial clock (sclk) l system/self-calibration with r/w registers l power supply configurations - va+ = +5 v; va- = 0 v; vd+ = +3 v to +5 v - va+ = +2.5 v; va- = -2.5 v; vd+ = +3 v to +5 v l low power consumption: 2.5 mw general description the 16-bit cs5529 is a low-power programmable ds an- alog-to-digital converter (adc) which includes coarse/fine charge buffers, a fourth order ds modulator, a calibration microcontroller, a digital filter with program- mable decimation rates, a 6-bit output latch, and a three- wire serial interface. the adc is designed to operate from single or dual analog supplies and a single digital supply. the digital filter is programmable with output update rates between 1.88 hz to 101 hz. these output rates are specified for xin = 32.768 khz. output word rates can be increased by approximately 3x by using xin = 100 khz. the filter is designed to settle to full accuracy for the se- lected output word rate in one conversion. when operated at word rates of 15 hz or less, the filter rejects both 50 hz and 60 hz simultaneously. low power, single conversion settling time, programma- ble output rates, and the ability to handle negative input signals make this single or dual supply product an ideal solution for isolated and non-isolated applications. ordering information see page 27. va+ ain+ ain- vref+ vref- latch a0 a1 d0 d1 d2 d3 calibration memory calibration m c clock gen. xin xout va- dgnd 1x 1x differential 4th order delta-sigma modulator digital filter calibration register control register output register vd+ cs sclk sdi sdo mar 99 ds246f1
cs5529 2 ds246f1 table of contents table of contents ....................................................................................... 2 table of figures .......................................................................................... 3 characteristics/specifications ............................................................ 4 analog characteristics................................................................... 4 5 v digital characteristics ............................................................. 6 3 v digital characteristics ............................................................. 6 dynamic characteristics ................................................................. 6 absolute maximum ratings .............................................................. 7 switching characteristics ............................................................. 8 general description ................................................................................ 10 analog input ............................................................................................. 10 analog input model ............................................................................ 10 voltage reference input model .......................................................... 10 serial port ................................................................................................. 11 command register descriptions ........................................................ 12 serial port interface ........................................................................... 13 serial port initialization ....................................................................... 15 system initialization ........................................................................... 15 configuration register .............................................................................. 15 latch output pins ............................................................................... 15 power consumption ........................................................................... 15 output word rate .............................................................................. 16 digital filter ........................................................................................ 16 clock generator ................................................................................. 16 reset system ..................................................................................... 16 port flag ............................................................................................. 17 calibration .......................................................................................... 17 calibration registers ................................................................... 17 offset register ...................................................................... 17 gain register ........................................................................ 18 self calibration ............................................................................ 18 system calibration ....................................................................... 18 limitations in calibration range .................................................. 19 calibration tips ............................................................................ 19 configuration register descriptions ................................................. 20 performing conversions ........................................................................... 21 performing conversions with pf bit = 0 ............................................. 21 performing conversions with pf bit = 1 ............................................. 21 single conversion ........................................................................ 21 continuous conversions .............................................................. 21 output coding .................................................................................... 22 power supply arrangements .................................................................... 23 pcb layout .............................................................................................. 24 pin descriptions ......................................................................................... 25 clock generator......................................................................................... 25 control pins and serial data i/o................................................................ 25 measurement and reference inputs ......................................................... 26 power supply connections........................................................................ 26 specification definitions ........................................................................ 27 ordering guide ............................................................................................ 27 package dimensions ................................................................................. 28
cs5529 ds246f1 3 table of figures input models for ain+ and ain- pins......................................................... 11 input model for vref+ and vref- pins. .................................................. 11 cs5529 register diagram. ....................................................................... 11 command and data word timing. ............................................................ 14 filter response (normalized to output word rate = 1)............................ 16 self calibration of offset. .......................................................................... 18 self calibration of gain. ............................................................................ 18 system calibration of offset...................................................................... 18 system calibration of gain........................................................................ 19 cs5529 configured with a +5.0 v analog supply..................................... 23 cs5529 configured with 2.5 v analog supplies. .................................... 23 spi? is a trademark of motorola inc., microwire? is a trademark of national semiconductor corp. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and i s provided as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for infringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyr ights, trademarks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any mean s (electronic, mechanical, pho- tographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk m ay be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, i n any form or by any means (elec- tronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of ci rrus logic, inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trademarks and service marks can be found at http://www.cirrus.com.
cs5529 4 ds246f1 characteristics/specifications analog characteristics (t a = 25 c; va = 2.5 v 5%, vd+ = 5 v 5%, vref+ = 2.5 v, vref- = 0.0 v, f clk = 32.768 khz, owr (output word rate) = 15 hz, bipolar mode, input range = 2.5 v.) (see notes 1 and 2.) notes: 1. applies after system calibration at any temperature within -40 c ~ +85 c. 2. specifications guaranteed by design, characterization, and/or test. 3. specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. drift over specified temperature range after calibration at power-up at 25 c. 5. wideband noise aliased into the baseband. referred to the input. typical values shown for 25 c. 6. for peak-to-peak noise multiply by 6.6 for all ranges and output rates. specifications are subject to change without notice. parameter min typ max unit accuracy linearity error - 0.0015 0.003 %fs no missing codes 16 - - bits bipolar offset (note 3) - 1 2 lsb 16 unipolar offset (note 3) - 2 4 lsb 16 offset drift (notes 3 and 4) - 11 - nv/c bipolar gain error - 8 31 ppm unipolar gain error - 16 63 ppm gain drift (note 4) - 1 - ppm/c noise (notes 5 and 6) output word rate (hz) -3 db filter frequency (hz) noise (v) 1.88 1.64 4.5 3.76 3.27 5.0 7.51 6.55 7.0 15.0 12.7 15 30.0 25.4 45 61.6 50.4 190 84.5 70.7 900 101.1 84.6 3000
cs5529 ds246f1 5 analog characteristics (continued) notes: 7. see the section of the data sheet which discusses analog input models. 8. the minimum full scale calibration range (fscr) is limited by the maximum allowed gain register value (with margin). the maximum fscr is limited by the ds modulators 1s density range. see analog input section for details. also see limitations in calibration range. 9. vref must be less than or equal to supply voltages. 10. all outputs unloaded. all inputs cmos levels. parameter min typ max unit analog input common mode + signal on ain+ or ain- (bipolar/unipolar mode) single supply dual supply 0.0 va- - - va+ va+ v v common mode rejection dc 50, 60hz - - 120 120 - - db db input capacitance - 10 - pf cvf current ain+, ain- (note 7) - 16 - na system calibration specifications full scale calibration range, with vref = 2.5 v (note 8) 1.0 - 3.5 v offset calibration range (bipolar/unipolar mode) - - 1.25 v voltage reference input range {(vref+) - (vref-)} (note 9) 1.0 2.5 5 v ref+ va- - va+ v ref- va- - va+ v common mode rejection dc 50, 60 hz - - 110 130 - - db db input capacitance - 16 - pf cvf current (note 7) - 8 - na power supplies dc power supply currents (normal mode) i a+ i d+ - - 360 95 450 150 a a power consumption normal mode (note 10) low power mode standby sleep - - - - 2.5 1.4 1 500 2.875 2.2 - - mw mw mw w power supply rejection dc positive supplies dc negative supply - - 80 80 - - db db
cs5529 6 ds246f1 5 v digital characteristics (t a = 25 c; va = 2.5v 5%, vd+ = 5v 5%.)(see notes 2 and 11.) notes: 11. all measurements performed under static conditions. 12. i out = -100 a unless stated otherwise. (v oh = 2.4 v @ i out = -40 a). 3 v digital characteristics (t a = 25 c; va = 2.5 v 5%, vd+ = 3.0 v 5%.) (see notes 2 and 11.) dynamic characteristics parameter symbol min typ max unit high-level input voltage: all pins except xin, sclk xin sclk v ih v ih v ih 0.6vd+ (vd+)-0.9 (vd+)-0.45 - - - - - - v v v low-level input voltage: all pins except xin, sclk xin sclk v il v il v il - - - - - - 0.8 2.0 0.6 v v v high-level output voltage: all pins except sdo (note 12) sdo, i out = -5.0ma v oh v oh (vd+)-1.0 (vd+)-1.0 - - - - v v low-level output voltage: all pins except sdo, i out = 1.6ma sdo, i out = 5.0ma v ol v ol - - - - 0.4 0.4 v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol min typ max unit high-level input voltage: all pins except xin, sclk xin sclk v ih v ih v ih 0.6vd+ (vd+)-0.9 (vd+)-0.45 - - - - - - v v v low-level input voltage: all pins except xin, sclk xin sclk v il v il v il - - - - - - 0.16 vd+ 0.5 0.6 v v v high-level output voltage: all pins except sdo, i out = -400 a sdo, i out = -5.0 ma v oh v oh (vd+)-0.3 (vd+)-1.0 - - - - v v low-level output voltage: all pins except sdo, i out = 400 a sdo, i out = 5.0 ma v ol v ol - - - - 0.3 0.4 v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -9-pf parameter symbol ratio units modulator sampling frequency f s xin/4 hz filter settling time to 1/2 lsb (full scale step) t s 1/f out s
cs5529 ds246f1 7 absolute maximum ratings (dgnd = 0 v) (see note 13.) notes: 13. all voltages with respect to ground. 14. va+ and va- must satisfy {(va+) - (va-)} +6.0 v. 15. vd+ and va- must satisfy {(vd+) - (va-)} +7.75 v. 16. applies to all pins including continuous overvoltage conditions at the analog input (ain) pins. 17. transient current of up to 100ma will not cause scr latch-up. maximum input current for a power supply pin is 50 ma. 18. total power dissipation, including all input currents and output currents. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit dc power supplies (notes 14 and 15) positive digital positive analog negative analog vd+ va+ va- -0.3 -0.3 -6.0 - - - +6.0 +6.0 +0.3 v v v input current, any pin except supplies (notes 16 and 17) i in --10ma output current i out --25ma power dissipation (note 18) pdn - - 8 mw analog input voltage ain and vref pins v ina (va-) + (-0.3) - (va+)+0.3 v digital input voltage v ind -0.3 - (vd+)+0.3 v ambient operating temperature t a -40 - +85 c storage temperature t stg -65 - +150 c
cs5529 8 ds246f1 switching characteristics (t a = 2 5 c ; v a = 2 . 5 v 5 % , v d + = 3 v 5 % o r 5 v 5 % ; input levels: logic 0 = 0 v, logic 1 = vd+; c l = 50pf) notes: 19. device parameters are specified with 32.768 khz clock, however, clocks up to 100 khz can be used for increased throughput. 20. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 21. oscillator start-up time varies with crystal parameters. this specification does not apply when using an external clock source. parameter symbol min typ max unit master clock frequency: external clock or internal oscillator (note19) xin 30 32.768 100 khz master clock duty cycle 40 - 60 % rise times (note 20) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns fall times (note 20) any digital input except sclk sclk any digital output t rise - - - - - 50 1.0 100 - s s ns start-up oscillator start-up time xtal = 32.768 khz (note 21) t ost -500-ms power-on reset period t por - 1002 - xin cycles serial port timing serial clock frequency sclk 0 - 2 mhz serial clock pulse width high pulse width low t 1 t 2 250 250 - - - - ns ns sdi write timing cs enable to valid latch clock t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk falling prior to cs disable t 6 100 - - ns sdo read timing cs to data valid t 7 --150ns sclk falling to new data bit t 8 --150ns cs rising to sdo hi-z t 9 --150ns
cs5529 ds246f1 9 continuous running sclk timing (not to scale) cs sclk t3 t6 t2 t1 sdi write timing (not to scale) cs sclk msb msb-1 lsb sdi t3 t6 t4 t5 t1 t2 sdo read timing (not to scale) cs sclk msb msb-1 lsb sdo t7 t9 t8 t1 t2
cs5529 10 ds246f1 general description the cs5529 is a 16-bit ds analog-to-digital con- verter (adc) which includes coarse/fine charge buffers, a fourth order ds modulator, a calibration microcontroller, eight digital filters which provide selectable decimation rates, a 6-bit output latch, and a three-wire serial interface. the adc is opti- mized to digitize unipolar or bipolar signals in in- dustrial applications. the digital filters provide eight selectable output word rates (owrs) of 1.88 hz, 3.76 hz, 7.51 hz, 15.0 hz, 30.0 hz, 61.6 hz, 84.5 hz, 101.1 hz when operated from a 32.768 khz watch crystal or equiv- alent clock (output word rates can be increased by approximately 3x by using 100 khz clock). the filters are designed to settle to full accuracy for the selected output word rate in one conversion. when operated at word rates of 15 hz or less (xin = 32.768 khz), the filter rejects both 50 hz and 60 hz line interference simultaneously. analog input the cs5529 provides a nominal 2.5 v input span when the gain register is 1.0 decimal and the differ- ential reference voltage between vref+ and vref- is 2.5 v. the gain registers content is used during calibration to set the gain slope of the adcs transfer function. the differential reference voltage magnitude and the gain register are two factors that can be used to scale the nominal 2.5 v input span. after reset, the gain register defaults to 1.0 decimal. in this case, the external voltage be- tween the vref+ pin and the vref- pin sets the adcs nominal full scale input span to 2.5 v. if a user want to modify the input span, either the gain register or the reference voltages magnitude needs to be changed. for example, if a 1.25 v reference is used in place of the nominal 2.5 v input, the full- scale span is cut in half. to achieve the same 1.25v input span, the user could simply use a 2.5 v refer- ence and modify the gain register to 2.0 decimal. note that to keep from saturating the analog front end, the input span must stay at or below 1.5 times the reference voltage. this corresponds to a gain register of 0.666... when a 2.5 v reference voltage is used. note: when a smaller reference voltage is used, the resulting code widths are smaller. since the output codes exhibit more changing codes for a fixed amount of noise, the converter appears noisier. calibration can also affect the adcs full scale span because system gain calibration can be used to increase or decrease the full scale span of the adcs transfer functions. at its limit, the input full scale can be reduced to the point in which the gain register reaches its upper limit of 3.999... (this will occur when the adc is gain calibrated with an in- put signal less than or equal to approximately 1/4 of its nominal full scale, if the adc does not have in- trinsic gain error). calibration and its effects on the analog input span is detailed in a later section of the data sheet. analog input model figure 1 illustrates the input models for the ain pins. the model includes a coarse/fine charge buff- er which reduces the dynamic current demands from the signal source. the buffer is designed to accommodate rail to rail (common-mode plus sig- nal) input voltages. typical cvf (sampling) cur- rent is about 16na (xin = 32.768 khz, see figure 1). application note 30, switched-capacitor a/d input structures, details various input architec- tures. voltage reference input model figure 2 illustrates the input models for the vref pins. it includes a coarse/fine charge buffer which reduces the dynamic current demand of the exter- nal reference. typical cvf (sampling) current is about 8na (xin = 32.768 khz, see figure 2). the references buffer is designed to accommodate rail-to-rail (common-mode plus signal) input volt-
cs5529 ds246f1 11 ages. the differential voltage between vref+ and vref- sets the nominal full scale input span of the converter. for a single-ended reference voltage, such as the lt1019-2.5, the reference output is connected to the vref+ pin of the cs5529 and the ground reference for the lt1019-2.5 is connected to the vref- pin. serial port the cs5529 includes a microcontroller with a command register, a configuration register, a con- version data register (read only), and a gain and off- set register for calibration. all registers, except the 8-bit command register, are 24-bits in length. fig- ure 3 illustrates a block diagram of all the internal register. after a system initialization or reset, the serial port is set to the command mode. the converter stays in this mode until a valid 8-bit command is received (the first 8-bits into the serial port). once a valid 8- bit command is received and interpreted by the adcs command register, the serial port enters the data mode. in data mode the next 24 serial clock pulses shift data either into or out of the serial port (72 serial clock pulses are needed if the setup reg- ister command is issued). the command register descriptions section illustrates all valid com- mands. ain c = 20pf f = 32.768 khz f coarse 1 f fine 1 v 25mv i = fv c os os n figure 1. input models for ain+ and ain- pins. vref c = 10pf f = 32.768 khz 2 f fine 1 v 25mv i = fv c os os n f coarse figure 2. input model for vref+ and vref- pins. latch outputs low power mode output word rates unipolar/bipolar reset system etc. configuration register (1 24) serial interface cs sdi sdo sclk command register (1 8) write only read only conversion data register (1x24) gain register (1 24) offset register (1 24) figure 3. cs5529 register diagram.
cs5529 12 ds246f1 command register descriptions perform single conversion this command instructs the adc to perform a single conversion. perform continuous conversions this command instructs the adc to perform continuous conversions. power save/run if ps/r = 0, normal run mode is entered. if ps/r = 1, power save mode is entered. null this command is used to clear the port flag in the continuous conversion mode when the port flag bit in the configuration regis ter is set to logic 1. 76543210 11000000 76543210 10100000 76543210 1000000ps/r 76543210 00000000 table 1. command set d7(msb)d6d5d4d3d2d1d0 cb sc cc r/w rsb2 rsb1 rsb0 ps/r bit name value function d7 command bit, cb 0 1 null command (no operation). all command bits, including cb must be 0. logic 1 for executable commands. d6 single conversion, sc 0 1 single conversion not active. perform a conversion. d5 continuous conversions, cc 0 1 continuous conversions not active. perform conversions continuously. d4 read/write , r/w 0 1 write to selected register. read from selected register. d3-d1 register select bit, rsb2- rsb0 000 001 010 011 100 101 110 111 offset register gain register configuration register conversion data register (read only) set-up registers (offset, gain, configuration) reserved reserved reserved d0 power save/run , ps/r 0 1 run power save
cs5529 ds246f1 13 sync1 part of the serial port re-initialization sequence (see text for use of command). sync0 end of the serial port re-initialization sequence. read/write registers these commands are used to perform a write to or a read from a specific register. the register to be accessed is selected with the rsb2-rsb0 bits of the command word. r/w 0 write register 1 read register rsb[4:0] register address binary encoded 0 to 31 as follows. all registers are 24 bits long. address description 000 read or write offset register 001 read or write gain register 010 read or write configuration register 011 read conversion data register 100 read or write offset gain and configuration registers in this sequence (i.e. one 8-bit command is followed by 72-bits of data to access the offset, then the gain, and then the configuration register) serial port interface the cs5529s serial interface consists of four con- trol lines: cs , sdi, sdo, and sclk. cs , chip select, is the control line which enables access to the serial port. if the cs pin is tied to logic 0, the port can function as a three wire interface. sdi, serial data in, is the data signal used to trans- fer data to the converters. sdo, serial data out, is the data signal used to transfer output data from the converters. the sdo output will be held at high impedance any time cs is at logic 1. sclk, serial clock, is the serial bit-clock which controls the shifting of data to or from the adcs serial port. the cs pin must be held at logic 0 be- fore sclk transitions can be recognized by the port logic. to accommodate opto-isolators sclk is designed with a schmitt-trigger input to allow an opto-isolator with slower rise and fall times to di- rectly drive the pin. additionally, sdo is capable of sinking or sourcing up to 5 ma to directly drive an opto-isolator led. sdo will have less than a 400 mv loss in the drive voltage when sinking or sourcing 5 ma. figure 4 illustrates the serial sequence necessary to write to, or read from the serial ports registers. a transfer of data is always initiated by sending the appropriate 8-bit command (msb first) to the serial port (sdi pin). it is important to note that some commands use information from the configuration registers to perform the function. for those com- mands it is important that the correct information is written to the configuration register first. 76543210 11111111 76543210 11111110 76543210 100r/w rsb2 rsb1 rsb0 0
cs5529 14 ds246f1 command time 8 sclks data time 24 sclks (or 72 sclks for set-up registers) write cycle cs sclk sdi msb lsb command time 8 sclks cs sclk sdi data time 24 sclks (or 72 sclks for set-up registers) read cycle sdo msb lsb command time 8 sclks 8 sclks clear sdo flag sdo continuous conversion read (pf bit = 1) sdo sclk sdi t * d data time 24 sclks msb lsb * td = xin/owr clock cycles for each conversion except the first conversion which will take xin/owr + 7 clock cycles xin/owr clock cycles figure 4. command and data word timing.
cs5529 ds246f1 15 serial port initialization the serial port is initialized to the command mode whenever a power-on reset is performed or when the port initialization sequence is completed. the port initialization sequence involves clocking fif- teen (or more) sync1 command bytes (0xff) fol- lowed by one sync0 command byte (0xfe). this sequence places the chip in the command mode where it waits until a valid command is received. this function does not reset the internal registers to their default settings. it only resets the serial port to the command mode. system initialization when power to the cs5529 is applied, the chip is held in a reset condition until the 32.768 khz oscil- lator has started and a counter-timer elapses. due to the high q of the 32.768 khz crystal, the oscillator takes 400-600 ms to start. the counter-timer counts 1002 oscillator clock cycles to make sure the oscil- lator is fully stable. during this time-out period the serial port logic is reset and the rv (reset valid) bit in the configuration register is set to indicate that a valid reset occurred. after a reset, the on-chip registers are initialized to the following states and the converter is placed in the command mode where it waits for a valid command. note: a system reset can be initiated at any time by writing a logic 1 to the rs (reset system) bit in the configuration register. after a reset, the rv (reset valid) bit is set until the configuration register is read. the user must then write a logic 0 to the rs bit to take the part out of the reset mode. configuration register the configuration register is a 24 bit register used to modify the functions of the adc. the following sections detail the functions of the bits in the con- figuration register. latch output pins the d3-d0 pins of the converter mimic the d21- d18 bits of the configuration register. d3-d0 can be used to control multiplexers and other digital logic functions outside the converter. the d0-d3 outputs are powered from vd+ and dgnd. their output voltage will be vd+ for a logic 1 and dgnd for a logic 0. the a1-a0 pins of the con- verter mimic the d23-d22 bits of the configuration register and can be used to control analog switches. these outputs are powered from va+ and va-, hence, their output voltage will be either va+ for a logic 1 or va- for a logic 0. all outputs can sink or source at least 1 ma, but it is recommended to limit drive currents to less than 20 m a to reduce self-heating of the chip. power consumption the cs5529 accommodates four power consump- tion modes: normal, low power, standby, and sleep. the normal mode, the default mode, is entered after a power-on-reset and typically consumes 2.5 mw. the low power mode is an alternate mode that re- duces the consumed power to 1.4 mw. it is entered by setting bit d16 (the low power mode bit) in the configuration register to logic 1. since the convert- ers noise and linearity performance improves with increased power consumption, slightly degraded noise or linearity performance should be expected in the low power mode. the final two modes are the power save modes. these modes power down most of the analog por- tion of the chip and stop filter convolutions. the power save modes are entered whenever the power save (0x81 hexadecimal) command is issued to the serial port. the particular power save mode entered depends on state of bit d4 (the power save select bit) in the configuration register. if d4 is logic 0, the converter enters the standby mode reducing the power consumption to 1 mw. the standby mode leaves the oscillator and the on-chip bias generator configuration register: 000040(h) offset register: 000000(h) gain register: 400000(h)
cs5529 16 ds246f1 running. this allows the converter to quickly return to the normal or low power mode once the ps/r bit is set back to a logic 0. if d4 in the configuration register is logic 1 and power save command is is- sued, the sleep mode is entered reducing the con- sumed power to less than 10 w. since the sleep mode disables the oscillator, approximately a 500 ms crystal oscillator start-up delay period is re- quired before returning to the normal or low power mode. if an external clock is used, the chip should start within a few microseconds. output word rate the wr2-wr0 bits of the configuration register set the output conversion word rate of the converter as shown in the configuration register descrip- tions table. the word rates indicated in the table as- sume a master clock of 32.768 khz. upon reset the converter is set to operate with an output word rate of 15.0 hz. digital filter the cs5529 has eight different linear phase digital filters which set the output word rates (owrs) as stated in configuration register descriptions. these rates assume that xin is 32.768 khz. each of the filters has a magnitude response similar to that shown in figure 5. the filters are optimized to settle to full accuracy every conversion and yield better than 80 db rejection for both 50 hz and 60 hz with output word rates at or below 15.0 hz (xin = 32.768 khz). the converters digital filters scale with xin. for example with an output word rate of 15 hz, the fil- ters corner frequency is typically 12.7 hz. if xin is increased to 64.536 khz the owr doubles and the filters corner frequency moves to 25.4 hz. clock generator the cs5529 includes a gate which can be connect- ed with an external crystal to provide the master clock for the chip. the chip is designed to operate using a low-cost 32.768 khz tuning fork type crystal. one lead of the crystal should be connected to xin and the other to xout. lead lengths should be minimized to reduce stray capacitance. note that the converter will operate with an exter- nal (cmos compatible) clock with frequencies up to 100 khz. reset system the reset system bit permits the user to perform a hardware reset. a hardware reset can be initiated at any time by writing a logic 1 to the rs (reset sys- tem) bit in the configuration register. after a hard- ware reset cycle is complete, the serial port logic is reset and the rv (reset valid) bit in the configura- tion register is set to indicate that a valid reset oc- curred. after a reset, the on-chip registers are initialized to the following states and the converter is placed in the command mode where it waits for a valid command. note: a system reset can be initiated at any time by writing a logic 1 to the rs (reset system) bit in the configuration register. after a reset, the rv (reset valid) bit is set until the configuration register is read. the user must then write a logic 0 to the rs bit to take the part out of the reset mode. figure 5. filter response (normalized to output word rate = 1). configuration register: 000040(h) offset register: 000000(h) gain register: 400000(h)
cs5529 ds246f1 17 port flag the port flag bit in the configuration register allows the user to select the mode in which conversions will be presented to the serial port. with the port flag bit cleared, the user must read the conversion data register. with the port flag bit set to logic 1, the user can read the conversion data from the serial port by first issuing the null command to clear the sdo flag and then issuing 24 sclks to read the conversion word. calibration calibration is used to set the zero and gain slope of the adcs transfer function. the calibration con- trol bits in the configuration register allow the user to perform either self calibration or system calibra- tion. the offset and gain calibration steps each take one conversion cycle to complete. at the end of the cal- ibration step, the calibration control bits will be set back to logic 0, and the df (done flag) bit will be set to a logic 1. for the combination self-calibration (cc2-cc0= 011; offset calibration followed by gain calibration), the calibration will take two con- version cycles to complete and will set the df bit after the gain calibration is completed. note: 1) the df bit will be cleared any time the data register, the offset register, the gain register, or the setup register is read. reading the configuration register alone will not clear the df bit. 2) after the cs5529 is reset, the converter is functional and can perform measurements without being calibrated. in this case, the converter will utilize the initialized values of the on-chip registers (gain = 1.0, offset = 0.0) to calculate output words. any initial offset and gain errors in the internal circuitry of the chip will remain. calibration registers the offset calibration result is stored in the offset register. the result is used during the conversion process to nullify offset errors. one lsb in the off- set register is 2 -24 proportion of the input span (bi- polar span is 2 times the unipolar span). the msb in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 nega- tive). the converter can typically trim 50 percent of the input span. refer to the following offset register and gain register descriptions for details. offset register one lsb represents 2 -24 proportion of the input span (bipolar span is 2 times unipolar span). offset and data word bits align by msb (bit msb-4 of offset register changes bit msb-4 of data). after reset, all bits are 0. 23(msb)2221201918171615141312 sign 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 000000000000 11109876543210 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 000000000000
cs5529 18 ds246f1 gain register the gain register span is from 0 to (4-2 -22 ). after reset the (msb-1) bit is 1, all other bits are 0. the gain calibration results is stored in the gain register. the result sets the slope of the adcs transfer function. the gain register spans from 0 to (4 - 2 -22 ). the decimal equivalent meaning of the gain register is where the binary numbers have a value of either zero or one (b 0 corresponds to bit msb-1, n = 22). self calibration the cs5529 offers both self offset and self gain calibrations. for the self-calibration of offset, the converter internally ties the inputs of the modulator together and routes them to the vref- pin as shown in figure 6. also self offset calibration re- quires that vref- be tied to a fixed voltage be- tween va+ and va-. for self-calibration of gain, the differential inputs of the modulator are connect- ed to vref+ and vref- as shown in figure7. system calibration for the system calibration functions, the user must input signals which represent system ground and system full scale to the converter. when a system offset calibration is performed a ground reference signal must be applied to the converter (see figure 8). when a system gain calibration is performed, the user must input a signal representing the posi- tive full scale point as shown in figure 9. in either case, calibration signals must be within the speci- fied calibration limits for each specific calibration step (refer to the system calibration specifica- 23(msb)2221201918171615141312 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 000000000000 11109876543210 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 000000000000 db msb 2 1 b ( 0 2 0 b 1 2 1 C ? b n 2 n C ) ++++ b msb 2 1 b i 2 i C i 0 = n ? + == ain+ ain- s1 open + - s2 open s4 closed vref- s3 closed figure 6. self calibration of offset. ain+ ain- open + - open closed vref+ closed vref- + - reference figure 7. self calibration of gain. + - external connections 0v + - ain+ ain- figure 8. system calibration of offset.
cs5529 ds246f1 19 tions). if a system gain calibration is performed, the calibrated input must not cause the resulting gain registers content, decoded in decimal, to exceed 3.9999998. the above condition requires that the full scale input voltage to be greater than 25 percent of the differential reference voltage (i.e. a 625mv input signal must be applied if the differential ref- erence voltage is 2.5v). limitations in calibration range system calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the analog input section of this data sheet. for gain calibration the full scale input signal can be reduced to the point in which the gain register reaches its upper limit of (4-2 -22 decimal) or ffffff (hexadecimal). under nominal condi- tions, this occurs with a full scale input signal equal to about 1/4 the reference voltage. with the con- verters intrinsic gain error, this full scale input sig- nal may be higher or lower. in defining the minimum full scale calibration range (fscr) under analog characteristics, margin is retained to accommodate the intrinsic gain error. alterna- tively the input full scale signal can be increased to a point which exceeds the operating range of the analog circuitry. this occurs when the input volt- age is approximately 1.5x the differential refer- ence voltage (gain register = 1.0). calibration tips calibration steps are performed at the output word rate selected by the wr2-wr0 bits of the configu- ration register. since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. also, to minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port. factory calibration can be performed in a users system by using the system calibration capabilities of the cs5529. after the adc is calibrated in the users system, the offset and gain register contents can be read by the system microcontroller and re- corded in eeprom. these same calibration words can then be uploaded into the offset and gain regis- ters of the converter when power is first applied to the system. a user can scale the input range by modifying the gain register. for example, if a self or system cali- bration is performed with a full scale of 2.5 v and a full scale of 1.25 v is desired, the user can modify the gain register to double its slope. this can be done by reading the gain register, shifting the bina- ry word one position to the left (this multiplies the gain word by 2), and writing this word back into the gain register. the gain register can be scaled by any amount as long as it does not exceed a decimal range of 0.25 to 4.0. one of two methods can be used to determine when a calibration is complete: 1) if the pf (port flag) bit of the configuration register is set to logic 1, sdo falls to logic 0 at the completion of a calibration; or 2) regardless of the pf bit, the df (done flag) bit in the configuration register is set at completion of calibration. the user can either monitor the df bit or sdo to determine when a calibration is com- plete. whichever method is used, the calibration control bits (cc2-cc0) automatically return to log- ic 0 upon completion of any calibration. + - external connections full scale + - ain+ ain- figure 9. system calibration of gain.
cs5529 20 ds246f1 configuration register descriptions d23(msb) d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 a1 a0 d3 d2 d1 d0 nu lpm wr2 wr1 wr0 u/b d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 nu nu nu nu rs rv pf pss df cc2 cc1 cc0 bit name value function d23-d22 latch outputs, a1-a0 00 r* latch output pins a1-a0 mimic the d23-d22 register bits. d21-d18 latch outputs, d3-d0 0000 r* latch output pins d3-d0 mimic the d21-d18 register bits. d17 not used, nu 0 r must always be logic zero. d16 low power mode, lpm 0 1 r normal mode ( @ 2.5 mw) reduced power mode ( @ 1 mw) d15-d13 word rate, wr2-0 (note: rates valid for xin = 32.768 khz) 000 001 010 011 100 101 110 111 r 15.0 hz (2180 xin cycles) 30.0 hz (1092 xin cycles) 61.6 hz (532 xin cycles) 84.5 hz (388 xin cycles) 101.1 hz (324 xin cycles) 1.88 hz (17444 xin cycles) 3.76 hz (8724 xin cycles) 7.51 hz (4364 xin cycles) d12 unipolar/bipolar , u/b 0 1 r bipolar measurement mode unipolar measurement mode d11-d8 not used, nu 0 r must always be logic 0. d7 reset system, rs 0 1 r normal operation activate a reset cycle. to return to normal operation this bit must be written back to logic zero. d6 reset valid , rv 0 1r no reset has occurred or bit has been cleared (read only). valid reset has occurred. (cleared when read.) d5 port flag, pf 0 1 r port flag mode inactive port flag mode active d4 power save select, pss 0 1 r standby mode (oscillator active, allows quick power-up) sleep mode (oscillator inactive) d3 done flag, df 0 1 r done flag bit is cleared (read only). calibration or conversion cycle completed (read only). d2-d0 calibration control bits, cc2-cc0 000 001 010 011 100 101 110 111 r normal operation (no calibration) offset -- self-calibration gain -- self-calibration offset self-cal followed by gain self-calibration not used. offset -- system calibration gain -- system calibration not used. * r indicates the bit value after the part is reset
cs5529 ds246f1 21 performing conversions the cs5529 offers two modes of performing con- versions: single conversion and continuous conver- sions. the sections that follow detail the differences and provides examples illustrating how to use the modes. note that it is assumed that the configuration register has been initialized before conversions are performed. performing conversions with pf bit = 0 a single conversion is performed after the user transmits the single conversion command (0xc0 hexadecimal). at the completion of the conver- sion, the df (done flag) bit of the configuration register will be set to a logic 1. while the conver- sion is being performed, the user can read the con- figuration register to determine if the df bit is set. once df has been set, the read conversion data reg- ister command (0x96 hexadecimal) can be issued to read the conversion data register to obtain the conversion data word. note: 1)the df bit of the configuration register will be cleared to logic 0 when the conversion data register, the gain register, or the offset register is read. reading only the configuration register will not clear the df flag bit. 2) if another single conversion command is issued to the converter while it is performing a conversion, the filter will abandon the current conversion and restart a new convolution cycle. performing conversions with pf bit = 1 the pf (port flag) bit in the configuration register eliminates the need for the user to monitor the df (done flag) in the configuration register to deter- mine if the conversion is available. when pf is set to a logic 1, sdos output pin behaves as a flag sig- nal indicating when conversions are completed. sdo will fall to logic 0 once a new conversion is complete. single conversion a single conversion is performed after the user transmits the single conversion command (0xc0 hexadecimal). at the completion of the conver- sion, sdo will fall to logic 0 to indicate that the conversion is complete. to acquire the conversion, the user must issue 8 sclks with sdi = logic 0 (i.e. the null command) to clear the sdo flag. upon the falling edge of the 8th sclk, the sdo pin will present the first bit (msb) of the conver- sion word. 24 sclks (high, then low) are then re- quired to read the conversion word from the port. note: 1) the user must not give an explicit command (other than the null command) to read the conversion data register when the pf bit is set to logic 1. 2) the data conversion word must be read before a new command can be entered as the converter will remain in the data mode until the conversion word is read. 3) once the conversion is read the converter returns to the command mode. continuous conversions continuous conversions are performed after the user transmits the continuous conversions com- mand (0xa0 hexadecimal). at the completion of a conversion, sdo will fall to logic 0 to indicate that the conversion is complete. to read the conversion word, the user must issue 8 sclks with sdi = log- ic 0 (i.e. the null command) to clear the sdo flag. upon the falling edge of the 8th sclk, the sdo pin will present the first bit (msb) of the con- version word. 24 sclks (high, then low) are then required to read the conversion word from the port. when operating in the continuous conversion mode, the user need not read every conversion. if the user chooses not to read a conversion after sdo falls, sdo will rise one xin clock cycle before the next conversion word is available and then fall again to signal that another conversion word is available. to exit the continuous conversion mode, the user must issue any valid command, other than the null command, to the sdi input when the sdo flag falls. for instance, the user can just read
cs5529 22 ds246f1 the conversion data register again to exit the contin- uous conversion mode. note: 1) if the user begins to clear the sdo flag and read the conversion data, this action must be finished before the conversion cycle which is occurring in the background is complete if the user wants to be able to read the new conversion data. 2) if a cc command is issued to the converter while it is performing a conversion, the filter will stop the current conversion and start a new convolution cycle to perform a new conversion. 3) continuous conversions arent allowed unless the port flag bit is set in the configuration register. 4) the converter will remain in data mode and continually perform conversions until the exit command is issued (i.e. to exit the user must read a register). output coding as shown in the output conversion data register descriptions, the cs5529 presents output conver- sions as a 24-bit conversion word. the first 16 bits of the conversion word represent conversion data. the third byte contains two error flag bits. in the third byte, d7-d4 are always logic 1; d3-d2 are always logic 0; and bits d1-d0 are the two flag bits. the of (overrange flag) bit is set to a logic 1 any time the input signal is: 1) more positive than positive full scale, 2) more negative than zero (un- ipolar mode), 3) more negative than negative full scale (bipolar mode). it is cleared back to logic 0 whenever a conversion word occurs which is not overranged.the od (oscillation detect) bit is set to a logic 1 any time that an oscillatory condition is de- tected in the modulator. this does not occur under normal operating conditions, but may occur when- ever the input to the converter is extremely over- ranged. if the od bit is set, the conversion data bits can be completely erroneous. the od flag bit will be cleared to logic 0 when the modulator becomes sta- ble. table 2 and table 3 illustrate the output coding for the cs5529. unipolar conversions are output in bi- nary format and bipolar conversions are output two's complement. d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 msb1413121110987654 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 3 2 1 lsb 1 1 1 1 0 0 od of table 2. output conversion data register description (16 bits + flags). note: vfs in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. see text about error flags under overrange conditions. unipolar input voltage offset binary bipolar input voltage two's complement >(vfs-1.5 lsb) ffff >(vfs-1.5 lsb) 7fff vfs-1.5 lsb ffff ----- fffe vfs-1.5 lsb 7fff ----- 7ffe vfs/2-0.5 lsb 8000 ----- 7fff -0.5 lsb 0000 ----- ffff +0.5 lsb 0001 ----- 0000 -vfs+0.5 lsb 8001 ----- 8000 <(+0.5 lsb) 0000 <(-vfs+0.5 lsb) 8000 table 3. cs5529 16-bit output coding.
cs5529 ds246f1 23 power supply arrangements the cs5529 is designed to operate from single or dual analog supplies and a single digital supply. the following power supply connections are possi- ble: va+ = +5 v; va- = 0 v; vd+ = +3 v to +5 v va+ = +2.5 v; va- = -2.5 v; vd+ = +3 v to +5 v. figure 10 illustrates the cs5529 connected with a single +5 v supply to measure differential inputs relative to a common mode of 2.5 v. figure 11 il- figure 10. cs5529 configured with a +5.0 v analog supply. xout vd+ va+ vref+ vref- dgnd ain+ sclk sdo sdi cs5529 xin cs +5.0 v analog supply 20 19 3 213 10 11 9 14 15 8 12 optional clock source serial data interface 32.768 khz ~ 100 khz ain- 4 18 d3 d2 d1 d0 a1 a0 17 16 7 6 5 va- 1 5 v differential inputs (gain register = 1.0) 2.5 v differential inputs (gain register = 2.0) 1.25 v differential inputs (gain register = 4.0) logic outputs: a0, a1 switch from va+ to va- d0-d3 switch from vd+ to dgnd + - common mode = 0 to va+ 0.1 m f 0.1 m f 10 w figure 11. cs5529 configured with 2.5 v analog supplies. xout vd+ va+ vref+ vref- dgnd ain+ sclk sdo sdi cs5529 xin cs +2.5 v analog supply 20 19 3 213 10 11 9 14 15 8 12 optional clock source serial data interface 32.768 khz ~ 100 khz ain- 4 18 d3 d2 d1 d0 a1 a0 17 16 7 6 5 va- -2.5 v analog supply 1 2.5 v differential inputs (gain register = 1.0) 1.25 v differential inputs (gain register = 2.0) 625 mv differential inputs (gain register = 4.0) +3 v ~ +5 v digital supply logic outputs: a0, a1 switch from va+ to va- d0-d3 switch from vd+ to dgnd 0.1 m f 0.1 m f 0.1 m f
cs5529 24 ds246f1 lustrates the cs5529 connected with 2.5 v bipolar analog supplies and a +3 v to +5 v digital supply to measure ground referenced bipolar signals. pcb layout the cs5529 should be placed entirely over an ana- log ground plane with the dgnd pin of the device connected to the analog ground plane. place the an- alog-digital plane split immediately adjacent to the digital portion of the chip see the cdb5529 data sheet for suggested layout details and applications note 18 for more detailed layout guidelines. applications engineering pro- vides a free and confidential schematic review service.
cs5529 ds246f1 25 pin descriptions clock generator xin; xout - crystal in; crystal out, pins 10, 11. a gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. alternatively, an external (cmos compatible) clock (powered relative to vd+) can be supplied into the xin pin to provide the master clock for the device. control pins and serial data i/o cs - chip select, pin 8. when active low, the port will recognize sclk. when high the sdo pin will output a high impedance state. cs should be changed when sclk = 0. sdi - serial data input, pin 15. sdi is the input pin of the serial input port. data will be input at a rate determined by sclk. sdo - serial data output, pin 14. sdo is the serial data output. it will output a high impedance state if cs = 1. sclk - serial clock input, pin 9. a clock signal on this pin determines the input/output rate of the data for the sdi/sdo pins respectively. this input is a schmitt trigger to allow for slow rise time signals. the sclk pin will recognize clocks only when cs is low. 1 2 3 4 5 6 7 813 14 15 16 17 18 19 20 vref+ vref- d3 d2 d1 sdi sdo vd+ cs d0 a1 a0 ain- ain+ va+ va- 9 10 11 12 dgnd xin xout sclk voltage reference input voltage reference input logic output (digital) logic output (digital) logic output (digital) serial data input serial data output positive digital power digital ground crystal in chip select logic output (digital) logic output (analog) logic output (analog) differential analog input differential analog input positive analog power negative analog power crystal out serial clock input
cs5529 26 ds246f1 a0, a1 - logic outputs (analog), pin 5, 6. the logic states of a0-a1 mimic the states of the d22-d23 bits of the configuration register. logic output 0 = va-, and logic output 1 = va+. d0, d1, d2, d3 - logic outputs (digital), pin 7, 16, 17, 18. the logic states of d0-d3 mimic the states of the d18-d21 bits of the configuration register. logic output 0 = dgnd, and logic output 1 = vd+. measurement and reference inputs ain+, ain- - differential analog input, pins 3, 4. differential input pins into the device. vref+, vref- - voltage reference input, pins 20, 19. fully differential inputs which establish the voltage reference for the on-chip modulator. power supply connections va+ - positive analog power, pin 2. positive analog supply voltage. va- - negative analog power, pin 1. negative analog supply voltage. vd+ - positive digital power, pin 13. positive digital supply voltage (+3.0 v or +5 v). dgnd - digital ground, pin 12. digital ground.
cs5529 ds246f1 27 specification definitions linearity error the deviation of a code from a straight line which connects the two end points of the a/d converter transfer function. one end point is located 1/2 lsb below the first code transition and the other end point is located 1/2 lsb beyond the code transition to all ones. units in percent of full-scale. differential nonlinearity the deviation of a code's width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref+) - (vref-)} - 3/2 lsb]. units are in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above the voltage on the ain- pin). when in unipolar mode (u/b bit = 1). units are in lsbs. bipolar offset the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below the voltage on the ain- pin). when in bipolar mode (u/b bit = 0). units are in lsbs. ordering guide model number linearity error (max) temperature range package cs5529-ap 0.003% -40 c to +85 c 20-pin 0.3" plastic dip CS5529-AS 0.003% -40 c to +85 c 20-pin 0.2" plastic ssop
cs5529 28 ds246f1 package dimensions inches millimeters dim min max min max a 0.000 0.210 0.00 5.33 a1 0.015 0.025 0.38 0.64 a2 0.115 0.195 2.92 4.95 b 0.014 0.022 0.36 0.56 b1 0.045 0.070 1.14 1.78 c 0.008 0.014 0.20 0.36 d 0.980 1.060 24.89 26.92 e 0.300 0.325 7.62 8.26 e1 0.240 0.280 6.10 7.11 e 0.090 0.110 2.29 2.79 ea 0.280 0.320 7.11 8.13 eb 0.300 0.430 7.62 10.92 ec 0.000 0.060 0.00 1.52 l 0.115 0.150 2.92 3.81 0 15 0 15 20 pin plastic (pdip) package drawing e1 d seating plane b1 e b a l a1 top view bottom view side view 1 ea c a2 e ec eb
cs5529 ds246f1 29 notes: 1. d and e1 are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension b does not include dambar protrusion/intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of b dimension at maximum material condition. dambar intrusion shall not reduce dimension b by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.084 -- 2.13 a1 0.002 0.010 0.05 0.25 a2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 d 0.272 0.295 6.90 7.50 1 e 0.291 0.323 7.40 8.20 e1 0.197 0.220 5.00 5.60 1 e 0.022 0.030 0.55 0.75 l 0.025 0.041 0.63 1.03 0 8 0 8 20l ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
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